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ADC-30634/ADC-30720
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
FEATURES
* * * * * * * * * * 8-bit flash A/D converter 20MHz sampling rate 10MHz full-power bandwidth Sample-hold not required Low power CMOS +5Vdc operation 1.2 Micron CMOS 8-Bit latched outputs Surface-mount version No missing codes PIN
1 2 3 4 5 6 7 8 9 10 11 12
INPUT/OUTPUT CONNECTIONS
FUNCTION
VDD CLOCK INPUT -REFERENCE ANA/DIG GND (VSS) ANALOG INPUT REF MIDPOINT ANALOG INPUT ANA/DIG GND (VSS) +REFERENCE VDD N.C. N.C.
PIN
24 23 22 21 20 19 18 17 16 15 14 13
FUNCTION
BIT 8 (LSB) BIT 7 BIT 6 BIT 5 REF 1/4 FS VDD REF 3/4 FS BIT 4 BIT 3 BIT 2 BIT 1 (MSB) N.C.
GENERAL DESCRIPTION
The ADC-30634 and ADC-30720 utilizes an advanced VLSI 1.2 micron CMOS in providing 20MHz sampling rates at 8-bits. The flexibility of the design architecture and process delivers latch-up free operation without external components and operation over the full military range. The ADC-30634 and ADC-30720 are mechanically and electrically equivalent to the ADC-208LM and ADC208MM-QL, respectively, with the exception of the OVERFLOW (pin 13) and ENABLE (pins 11 and 12) functions. These functions are not offered on the ADC-30634 and ADC30720.
02 01
ANALOG INPUT
02 01
CLOCK GENERATOR
2
CLOCK
5,7
R2 +REFERENCE
9
D R G 1 Q
D G
Q
14
BIT 1
D G Q D G D G R2 Q 256 to 7 ENCODER D G
Q
15
BIT 2
3/4 REFERENCE
18
D G R
Q
16
BIT 3
1 R2 MIDPOINT REFERENCE
6
Q
17
BIT 4
1 1/4 REFERENCE
20
R2 D G D G R R2 Q D G Q Q
21
BIT 5
22
BIT 6
- REFERENCE
3
D D G Q G DIGITAL GND Q
PINS 1, 10, 19 +5V
+VDD
23
BIT 7
24
PINS 4-8 ANALOG GND
BIT 8 (LSB)
Figure 1. ADC-30634 and ADC-30720 Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com
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ADC-30634/ADC-30720
ABSOLUTE MAXIMUM RATINGS
PARAMETERS Power Supply Voltage (VDD Pin 1, 10, 19) Digital Inputs Analog Input Reference Inputs Digital Outputs (short circuit protected to ground) Lead Temperature (10 sec. max.) Storage Temperature FUNCTIONAL SPECIFICATIONS (Typical at +5V power, +25C, 20MHz clock, +REFERENCE = +5V, -REFERENCE = ground, unless noted) ANALOG INPUT Single-Ended, Non-Isolated Input Range DC - 20MHz Analog Input Capacitance (static - Pin 5 to 7) (dynamic - Pin 5 to 7) Reference Ladder Resistance Reference Input (Note 5) DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading Logic Loading "1" Logic Loading "0" Clock Low Pulse Width DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading Logic Loading "1" Logic Loading "0" Output Data Valid Delay From Rising Clock Edge 99% probability 100% probability +25C -55C to +125C Data Output Resolution Data Coding PERFORMANCE Sampling Rate Full Power Bandwidth Diff. Linearity @ +25C (See tech note 7) Code Transitions Center of Codes Diff. Linearity Over Temp. Code Transitions Center of Codes Int. Linearity @ +25C (See tech note 4)(ref. adjusted) End-point Best-fit Line Int. Linearity Over Temp. (ref. adjusted) Best-fit Line Int. Linearity @ +25C (ref. unadjusted) End-point Best-fit Line 15 10 -- -- -- -- -- -- -- -- -- 20 -- 0.5 0.25 0.5 0.25 -- -- 1/2 2 1.6 -- -- 1.0 -- 1.0 -- 1/2 1/2 1 2.5 1.9 MSPS MHz LSB LSB LSB LSB LSB LSB LSB LSB LSB 2.4 -- 4 4 5 5 -- 8 4.5 -- -- -- 10 5.0 0.4 -- -- 15 Volts Volts mA mA nSec nSec nSec Bits Footnotes: Maximum input impedance is a function of clock frequency. At full-power input. For 10-step, 40 IRE NTSC ramp test. 3.2 -- -- -- 15 -- -- +1 +1 25 -- 0.8 +5 +5 -- Volts Volts mA mA nSec MIN. 0 - - - -0.5 TYP. - 20 64 500 - MAX. +5.0 - - - VDD +0.5 UNITS Volts pF pF Ohms Volts LIMITS -0.5 to +7 -0.5 to +5.5 -0.5 to (+VDD +0.5) -0.5 to (+VDD +0.5) -0.5 to +5.5 +300 max. -65 to +150 UNITS Volts Volts Volts Volts Volts C C PERFORMANCE Int. Linearity Over Temp. (ref. unadjusted) End-point Best-fit Line Zero-Scale Offset (Code "0" to "1" transition) Gain error, @ +25C Over Temperature Differential Gain Differential Phase Aperture Delay Aperture Jitter Harmonic Distortion (8MHz second order harm.) Ref. bandwidth (See tech note 5) Power Supply Rejection No Missing Codes POWER REQUIREMENTS Power Supply Range (+VDD) Power Supply Current +25C +125C -55C Power Dissipation +25C +125C -55C PHYSICAL ENVIRONMENTAL Operating Temp. Range, Case: MM/LM/QL Versions Storage Temp. Range Package Type DIP LCC -55 -65 -- -- +125 +150 C C +3.0 -- -- -- -- -- -- +5.0 +120 +100 +135 660 550 745 +5.5 +160 +125 +175 880 690 965 Volts mA mA mA mW mW mW MIN. TYP. MAX. UNITS
-- -- -- -- -- -- -- -- -- -40
2.3 1.8 2.5 1 1.5 2 1.1 8 50 -46
2.6 2.0 4 1.75 2.5 -- -- -- -- --
LSB LSB LSB LSB LSB % degrees ns ps dB
-- 10 -- MHz -- 0.02 0.05 %FSR/%Vs Over the operating temperature range
24-pin ceramic DIP 24-pin ceramic LCC
10 25 -- 40 -- -- Straight binary
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD and may be referenced anywhere within the specified limits. AC modulation of the reference voltage may also be utilized; contact DATEL for further information. 2. Clock Pulse Width - To improve performance when input signals may exceed Nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the input voltage slews and prevents the comparators from saturating. 3. A full-scale input produces all "1" on the data outputs.
4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and Differential Linearity (code transition). The specifications using the less conservative definition have also been provided as a comparative specification for products specified this way.
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com
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ADC-30634-30720
5. The process that is used to fabricate the ADC30634/30720 eliminates the latchup phenomena that has plagued CMOS devices in the past. These converters do not require external protection diodes. 6. For clock rates less than 100kHz, there may be some degradation in offset and differential nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). 7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2. Then apply an appropriate clock input.The reference input should be held to 0.1% accuracy or better. Do not use the +5V power supply as a reference without precision regulation and high-frequency decoupling capacitors. 8. Zero Adjustment - Adjusting the voltage at -REFERENCE (pin 3) adjusts the offset or zero of the device. Pin 3 can be tied to GROUND for operation without adjustments 9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment.
Table 1. ADC-30634/ADC-30720 Output Code ANALOG INPUT 0.00V +0.02V +1.28V +2.54V +2.56V +2.58V +3.84V +5.10V CODE Zero 0000 +1 LSB +1/4 FS +1/2 FS-ILSB +1/2 FS +1/2 FS+ILSB +3/4 FS +FS DATA 1234 0000 0000 0100 0111 1000 1000 1100 1111 DATA 5678 0000 0001 0000 1111 0000 0001 0000 1111 DECIMAL HEX 0 1 64 127 128 129 192 255 00 01 40 7F 80 81 C0 FF
Note: Values shown here are for a +5.12Vdc reference. Scale other refereces proportionally. (+REF=+5.12V, -REF=GND, 1/4, 1/2, and 3/4 References FS=No Connection)
10.Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral Nonlinearity through access of the reference's 1/4, 1/2, and 3/4 full scale points. For example, the REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE and -REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1F capacitors for operation without INL adjustments
+5V 4.7F +
+15 0.01F +5V D GND 4 A GND 8 VDD 1,10,19 0.1F + 4.7F
B8 B7 B6 B5 B4 B3 B2 B1
24 (LSB) 23 22 21 17 16 15 14 (MSB) 20
12 5 HA-5033 10 11 10
20MHz CLOCK
CLOCK 2
VIN 5,7
REF-3
-15 + +15V 2 2 6 LM324 REF. D2 4 4.7F 2k 3 5 10k 1+N + 1-N 1 +15V
REF+9
4.7F 0.1F
REF MID 6
HP2811
R1/4 R3/4 18
9 0.1F
1-N 8 LM324 + 1+N 4.7F 0.1F
10
1k 0.1F 1.5k 6 1-N 7 1k 0.1F 1.5k 12 1k 13 0.1F 2k 1+N 4.7F 1-N 14 LM324 + 0.1F LM324 5 1+N 4.7F + 0.1F
Figure 2. ADC-30634 and ADC-30720 Typical Connection Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * E-mail: sales@datel.com * Internet: www.datel.com
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ADC-30634/ADC-30720
MECHNICAL DIMENSIONS
ADC-30720 DIP
1.200 (30.5)
ADC-30634 LCC
0.250 0.005 (6.35) 0.050 (1.27) 0.595 (15.1) 0.610 (15.5) 0.400 SQ. +0.010, -0.005 (10.16) PIN 1 IDENTIFIER 0.020 0.005 (0.50) 0.100 (2.5) 0.325 (8.3) 0.090 Max. (2.28)
DATEL
ADC-30720
0.225 (5.7) 0.050 (1.3)
0.018 (0.5)
0.100 (2.5)
ORDERING INFORMATION
AUTO ZERO SAMPLE N 02 AUTO ZERO SAMPLE N+1 02 AUTO ZERO SAMPLE N+2 02
MODEL ADC-30720 ADC-30634
TEMP. RANGE -55C to +125C -55C to +125C
PACKAGE 24-pin DIP 24-pin LCC
01
01
01
N DATA
N+1 DATA
15nSec max.
15nSec max.
The ADC-30720 replaces the ADC-208MM-QL and includes DATEL QL High-Reliability Screening. The ADC-30634 replaces the ADC-208LM. Contact DATEL for availability of the other equivalent ADC-208 versions.
Figure 3 Timing Diagram
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DS-0500B
12/01
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: sales@datel.com
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-6354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.
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